/*
 * Copyright (c) 2010
 *	Ben Gray <ben.r.gray@gmail.com>.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 * 1. Redistributions of source code must retain the above copyright
 *    notice, this list of conditions and the following disclaimer.
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
 * 3. All advertising materials mentioning features or use of this software
 *    must display the following acknowledgement:
 *	This product includes software developed by Ben Gray.
 * 4. The name of the company nor the name of the author may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY BEN GRAY ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL BEN GRAY BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */


/**
 *	Functions to configure the PIN multiplexing on the chip.
 *
 *	This is different from the GPIO module in that it is used to configure the
 *	pins between modules not just GPIO input output.
 *
 */
#ifndef _OMAP3_PINMUX_H_
#define _OMAP3_PINMUX_H_



#define CONTROL_PADCONF_WAKEUP_EVENT     (1UL << 15)
#define CONTROL_PADCONF_WAKEUP_ENABLE    (1UL << 14)
#define CONTROL_PADCONF_OFF_PULL_UP      (1UL << 13)
#define CONTROL_PADCONF_OFF_PULL_ENABLE  (1UL << 12)
#define CONTROL_PADCONF_OFF_OUT_HIGH     (1UL << 11)
#define CONTROL_PADCONF_OFF_OUT_ENABLE   (1UL << 10)
#define CONTROL_PADCONF_OFF_ENABLE       (1UL << 9)
#define CONTROL_PADCONF_INPUT_ENABLE     (1UL << 8)
#define CONTROL_PADCONF_PULL_UP          (1UL << 4)
#define CONTROL_PADCONF_PULL_ENABLE      (1UL << 3)
#define CONTROL_PADCONF_MUXMODE_MASK     (0x7)



/* Active pin states */
#define PADCONF_PIN_OUTPUT              0
#define PADCONF_PIN_INPUT               CONTROL_PADCONF_INPUT_ENABLE
#define PADCONF_PIN_INPUT_PULLUP        ( CONTROL_PADCONF_INPUT_ENABLE \
                                        | CONTROL_PADCONF_PULL_ENABLE \
                                        | CONTROL_PADCONF_PULL_UP)
#define PADCONF_PIN_INPUT_PULLDOWN      ( CONTROL_PADCONF_INPUT_ENABLE \
                                        | CONTROL_PADCONF_PULL_ENABLE )

/* Off mode states */
#define PADCONF_PIN_OFF_NONE            0
#define PADCONF_PIN_OFF_OUTPUT_HIGH	    ( CONTROL_PADCONF_OFF_ENABLE \
                                        | CONTROL_PADCONF_OFF_OUT_ENABLE \
                                        | CONTROL_PADCONF_OFF_OUT_HIGH)
#define PADCONF_PIN_OFF_OUTPUT_LOW      ( CONTROL_PADCONF_OFF_ENABLE \
                                        | CONTROL_PADCONF_OFF_OUT_ENABLE)
#define PADCONF_PIN_OFF_INPUT_PULLUP    ( CONTROL_PADCONF_OFF_ENABLE \
                                        | CONTROL_PADCONF_OFF_PULL_ENABLE \
                                        | CONTROL_PADCONF_OFF_PULL_UP)
#define PADCONF_PIN_OFF_INPUT_PULLDOWN  ( CONTROL_PADCONF_OFF_ENABLE \
                                        | CONTROL_PADCONF_OFF_PULL_ENABLE)
#define PADCONF_PIN_OFF_WAKEUPENABLE	CONTROL_PADCONF_WAKEUP_ENABLE



/*
 *   bits 7:0    - mode
 *   bits 31:16  - register offset
 *
 */
#if 0

#define _PINMUX_PIN(off, mode)          (((off) << 16) | ((mode) & 0x7))
#define _PINMUX_PIN_MODE(pin)           (((pin) >> 16) & 0xFFFF)
#define _PINMUX_PIN_OFFSET(pin)         ((pin) & 0x7)

#define _PINMUX_PIN_DEF(name, off, mode) \
	name = _PINMUX_PIN(off, mode)

#define _MERGE(a,b) a ## b
#define _MERGE2(a,b) _MERGE(a,b)

#define _NA   _MERGE2(pinumx_reserved_,__COUNTER__)

#define _PINMUX_PIN_DEFEX(off, m0, m1, m2, m3, m4, m5, m6, m7) \
	m0 = _PINMUX_PIN(off, 0), \
	m1 = _PINMUX_PIN(off, 1), \
	m2 = _PINMUX_PIN(off, 2), \
	m3 = _PINMUX_PIN(off, 3), \
	m4 = _PINMUX_PIN(off, 4), \
	m5 = _PINMUX_PIN(off, 5), \
	m6 = _PINMUX_PIN(off, 6), \
	m7 = _PINMUX_PIN(off, 7)
	

enum pinumx_pin {
	_PINMUX_PIN_DEF(gpmc_a1, 0x007A, 0),  _PINMUX_PIN_DEF(gpio_34, 0x007A, 4),
	_PINMUX_PIN_DEF(gpmc_a2, 0x007C, 0),  _PINMUX_PIN_DEF(gpio_35, 0x007C, 4),
	_PINMUX_PIN_DEF(gpmc_a3, 0x007E, 0),  _PINMUX_PIN_DEF(gpio_36, 0x007E, 4),
	_PINMUX_PIN_DEF(gpmc_a4, 0x0080, 0),  _PINMUX_PIN_DEF(gpio_37, 0x0080, 4),
	_PINMUX_PIN_DEF(gpmc_a5, 0x0082, 0),  _PINMUX_PIN_DEF(gpio_38, 0x0082, 4),
	_PINMUX_PIN_DEF(gpmc_a6, 0x0084, 0),  _PINMUX_PIN_DEF(gpio_39, 0x0084, 4),
	_PINMUX_PIN_DEF(gpmc_a7, 0x0086, 0),  _PINMUX_PIN_DEF(gpio_40, 0x0086, 4),
	_PINMUX_PIN_DEF(gpmc_a8, 0x0088, 0),  _PINMUX_PIN_DEF(gpio_41, 0x0088, 4),
	_PINMUX_PIN_DEF(gpmc_a9, 0x008A, 0),  _PINMUX_PIN_DEF(gpio_42, 0x008A, 4),
	_PINMUX_PIN_DEF(gpmc_a10,0x008C, 0),  _PINMUX_PIN_DEF(gpio_43, 0x008C, 4),
	
	_PINMUX_PIN_DEF(gpmc_d0, 0x008E, 0),
	_PINMUX_PIN_DEF(gpmc_d1, 0x0090, 0),
	_PINMUX_PIN_DEF(gpmc_d2, 0x0092, 0),
	_PINMUX_PIN_DEF(gpmc_d3, 0x0094, 0),
	_PINMUX_PIN_DEF(gpmc_d4, 0x0096, 0),
	_PINMUX_PIN_DEF(gpmc_d5, 0x0098, 0),
	_PINMUX_PIN_DEF(gpmc_d6, 0x009A, 0),
	_PINMUX_PIN_DEF(gpmc_d7, 0x009C, 0),
	_PINMUX_PIN_DEF(gpmc_d8, 0x009E, 0), _PINMUX_PIN_DEF(gpio_44, 0x009E, 4),
	_PINMUX_PIN_DEF(gpmc_d9, 0x00A0, 0), _PINMUX_PIN_DEF(gpio_45, 0x00A0, 4),
	_PINMUX_PIN_DEF(gpmc_d10,0x00A2, 0), _PINMUX_PIN_DEF(gpio_46, 0x00A2, 4),
	_PINMUX_PIN_DEF(gpmc_d11,0x00A4, 0), _PINMUX_PIN_DEF(gpio_47, 0x00A4, 4),
	_PINMUX_PIN_DEF(gpmc_d12,0x00A6, 0), _PINMUX_PIN_DEF(gpio_48, 0x00A6, 4),
	_PINMUX_PIN_DEF(gpmc_d13,0x00A8, 0), _PINMUX_PIN_DEF(gpio_49, 0x00A8, 4),
	_PINMUX_PIN_DEF(gpmc_d14,0x00AA, 0), _PINMUX_PIN_DEF(gpio_50, 0x00AA, 4),
	_PINMUX_PIN_DEF(gpmc_d15,0x00AC, 0), _PINMUX_PIN_DEF(gpio_51, 0x00AC, 4),
	
	_PINMUX_PIN_DEF(gpmc_ncs0, 0x00AE, 0),
	_PINMUX_PIN_DEF(gpmc_ncs1, 0x00B0, 0), _PINMUX_PIN_DEF(gpio_52, 0x00B0, 4),
	_PINMUX_PIN_DEF(gpmc_ncs2, 0x00B2, 0), _PINMUX_PIN_DEF(gpio_53, 0x00B2, 4),
	_PINMUX_PIN_DEF(gpmc_ncs3, 0x00B4, 0), _PINMUX_PIN_DEF(gpio_54, 0x00B4, 4),
	_PINMUX_PIN_DEF(gpmc_ncs4, 0x00B6, 0),
		_PINMUX_PIN_DEF(mcbsp4_clkx,   0x00B6, 2),
		_PINMUX_PIN_DEF(gpt9_pwm_evt,  0x00B6, 3),
		_PINMUX_PIN_DEF(gpio_55,       0x00B6, 4),
	_PINMUX_PIN_DEF(gpmc_ncs5, 0x00B8, 0),
		_PINMUX_PIN_DEF(mcbsp4_dr,     0x00B8, 2),
		_PINMUX_PIN_DEF(gpt10_pwm_evt, 0x00B8, 3),
		_PINMUX_PIN_DEF(gpio_56,       0x00B8, 4),
	_PINMUX_PIN_DEF(gpmc_ncs6, 0x00BA, 0),
		_PINMUX_PIN_DEF(mcbsp4_dx,     0x00BA, 2),
		_PINMUX_PIN_DEF(gpt11_pwm_evt, 0x00BA, 3),
		_PINMUX_PIN_DEF(gpio_57,       0x00BA, 4),
	_PINMUX_PIN_DEF(gpmc_ncs7, 0x00BC, 0),
		_PINMUX_PIN_DEF(gpmc_io_dir,   0x00BC, 1),
		_PINMUX_PIN_DEF(mcbsp4_fsx,    0x00BC, 2),
		_PINMUX_PIN_DEF(gpt18_pwm_evt, 0x00BC, 3),
		_PINMUX_PIN_DEF(gpio_58,       0x00BC, 4),
	_PINMUX_PIN_DEF(gpmc_clk, 0x00BE, 0),
		_PINMUX_PIN_DEF(gpio_59,       0x00BE, 4),
	_PINMUX_PIN_DEF(gpmc_nbe0_cle, 0x00C6, 0), _PINMUX_PIN_DEF(gpio_60, 0x00C6, 4),
	_PINMUX_PIN_DEF(gpmc_nbe1,     0x00C8, 0), _PINMUX_PIN_DEF(gpio_61, 0x00C8, 4),
	_PINMUX_PIN_DEF(gpmc_nwp,      0x00CA, 0), _PINMUX_PIN_DEF(gpio_62, 0x00CA, 4),
	_PINMUX_PIN_DEF(gpmc_wait1,    0x00CE, 0), _PINMUX_PIN_DEF(gpio_63, 0x00CE, 4),
	_PINMUX_PIN_DEF(gpmc_wait2,    0x00D0, 0), _PINMUX_PIN_DEF(gpio_64, 0x00D0, 4),
	_PINMUX_PIN_DEF(gpmc_wait3,    0x00D2, 0), _PINMUX_PIN_DEF(gpio_65, 0x00D2, 4),
	
	

	/* MMC Pin multiplexing */
	_PINMUX_PIN_DEF(mmc1_clk, 0x0144, 0),
		_PINMUX_PIN_DEF(ms_clk,    0x0144, 1),
		_PINMUX_PIN_DEF(gpio_120,  0x0144, 4),
	_PINMUX_PIN_DEF(mmc1_cmd, 0x0146, 0),
		_PINMUX_PIN_DEF(ms_bs,     0x0146, 1),
		_PINMUX_PIN_DEF(gpio_121,  0x0146, 4),
	_PINMUX_PIN_DEF(mmc1_dat0, 0x0148, 0),
		_PINMUX_PIN_DEF(ms_dat0,   0x0148, 1),
		_PINMUX_PIN_DEF(gpio_122,  0x0148, 4),
	_PINMUX_PIN_DEF(mmc1_dat1, 0x014A, 0),
		_PINMUX_PIN_DEF(ms_dat1,   0x014A, 1),
		_PINMUX_PIN_DEF(gpio_123,  0x014A, 4),
	_PINMUX_PIN_DEF(mmc1_dat2, 0x014C, 0),
		_PINMUX_PIN_DEF(ms_dat2,   0x014C, 1),
		_PINMUX_PIN_DEF(gpio_124,  0x014C, 4),
	_PINMUX_PIN_DEF(mmc1_dat3, 0x014E, 0),
		_PINMUX_PIN_DEF(ms_dat3,   0x014E, 1),
		_PINMUX_PIN_DEF(gpio_125,  0x014E, 4),
	_PINMUX_PIN_DEF(mmc1_dat4, 0x0150, 0),
		_PINMUX_PIN_DEF(sim_io,    0x0150, 2),
		_PINMUX_PIN_DEF(gpio_126,  0x0150, 4),
	_PINMUX_PIN_DEF(mmc1_dat5, 0x0152, 0),
		_PINMUX_PIN_DEF(sim_clk,   0x0152, 2),
		_PINMUX_PIN_DEF(gpio_127,  0x0152, 4),
	_PINMUX_PIN_DEF(mmc1_dat6, 0x0154, 0),
		_PINMUX_PIN_DEF(sim_pwrctrl, 0x0154, 2),
		_PINMUX_PIN_DEF(gpio_128,    0x0154, 4),
	_PINMUX_PIN_DEF(mmc1_dat7, 0x0156, 0),
		_PINMUX_PIN_DEF(sim_rst,   0x0156, 2),
		_PINMUX_PIN_DEF(gpio_129,  0x0156, 4),
	
	_PINMUX_PIN_DEF(mmc2_clk, 0x0158, 0),
		_PINMUX_PIN_DEF(mcspi3_clk,  0x0158, 1),
		_PINMUX_PIN_DEF(gpio_130,    0x0158, 4),
	_PINMUX_PIN_DEF(mmc2_cmd, 0x015A, 0),
		_PINMUX_PIN_DEF(mcspi3_simo, 0x015A, 1),
		_PINMUX_PIN_DEF(gpio_131,    0x015A, 4),
	_PINMUX_PIN_DEF(mmc2_dat0, 0x015C, 0),
		_PINMUX_PIN_DEF(mcspi3_somi, 0x015C, 1),
		_PINMUX_PIN_DEF(gpio_132,    0x015C, 4),
	_PINMUX_PIN_DEF(mmc2_dat1, 0x015E, 0),
		_PINMUX_PIN_DEF(gpio_133,    0x015E, 4),
	_PINMUX_PIN_DEF(mmc2_dat2, 0x0160, 0),
		_PINMUX_PIN_DEF(gpio_134,    0x0160, 4),
	_PINMUX_PIN_DEF(mmc2_dat3, 0x0162, 0),
		_PINMUX_PIN_DEF(mcspi3_cs0,  0x0162, 1),
		_PINMUX_PIN_DEF(gpio_135,    0x0162, 4),
	_PINMUX_PIN_DEF(mmc2_dat4, 0x0164, 0),
		_PINMUX_PIN_DEF(mmc2_dir_dat0, 0x0164, 1),
		_PINMUX_PIN_DEF(mmc3_dat0,     0x0164, 3),
		_PINMUX_PIN_DEF(gpio_136,      0x0164, 4),
	_PINMUX_PIN_DEF(mmc2_dat5, 0x0166, 0),
		_PINMUX_PIN_DEF(mmc2_dir_dat1,    0x0166, 1),
		_PINMUX_PIN_DEF(cam_global_reset, 0x0166, 2),
		_PINMUX_PIN_DEF(mmc3_dat1,        0x0166, 3),
		_PINMUX_PIN_DEF(gpio_137,         0x0166, 4),
		_PINMUX_PIN_DEF(hsusb3_tll_stp,   0x0166, 5),
		_PINMUX_PIN_DEF(mm3_rxdp,         0x0166, 6),
		
	_PINMUX_PIN_DEFEX(0x0168, mmc2_dat6,   mmc2_dir_cmd,  cam_shutter,  mmc3_dat2,  gpio_138, hsusb3_tll_dir,   _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x016A, mmc2_dat7,   mmc2_clkin,   _NA,           mmc3_dat3,  gpio_139, hsusb3_tll_nxt,   mm3_rxdm,  _NA),
	_PINMUX_PIN_DEFEX(0x016C, mcbsp3_dx,   uart2_cts,    _NA,           _NA,        gpio_140, hsusb3_tll_data4, _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x016E, mcbsp3_dr,   uart2_rts,    _NA,           _NA,        gpio_141, hsusb3_tll_data5, _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x0170, mcbsp3_clkx, uart2_tx,     _NA,           _NA,        gpio_142, hsusb3_tll_data6, _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x0172, mcbsp3_fsx,  uart2_rx,     _NA,           _NA,        gpio_143, hsusb3_tll_data7, _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x0174, uart2_cts,   mcbsp3_dx,    gpt9_pwm_evt,  _NA,        gpio_144, _NA,              _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x0176, uart2_rts,   mcbsp3_dr,    gpt10_pwm_evt, _NA,        gpio_145, _NA,              _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x0178, uart2_tx,    mcbsp3_clkx,  gpt11_pwm_evt, _NA,        gpio_146, _NA,              _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x017A, uart2_rx,    mcbsp3_fsx,   gpt12_pwm_evt, _NA,        gpio_147, _NA,              _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x017C, uart1_tx,    _NA,          _NA,           _NA,        gpio_148, _NA,              _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x017E, uart1_rts,   _NA,          _NA,           _NA,        gpio_149, _NA,              _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x0180, uart1_cts,   _NA,          _NA,           _NA,        gpio_150, hsusb3_tll_clk,   _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x0182, uart1_rx,    _NA,          mcbsp1_clkr,   mcspi4_clk, gpio_151, _NA,              _NA,       _NA),
	_PINMUX_PIN_DEFEX(0x0184, mcbsp4_clkx, _NA,          _NA,           _NA,        gpio_152, hsusb3_tll_data1, mm3_txse0, _NA),
	_PINMUX_PIN_DEFEX(0x0186, mcbsp4_dr,   _NA,          _NA,           _NA,        gpio_153, hsusb3_tll_data0, mm3_rxrcv, _NA),
	_PINMUX_PIN_DEFEX(0x0188, mcbsp4_dx,   _NA,          _NA,           _NA,        gpio_154, hsusb3_tll_data2, mm3_txdat, _NA),
	_PINMUX_PIN_DEFEX(0x018A, mcbsp4_fsx,  _NA,          _NA,           _NA,        gpio_155, hsusb3_tll_data3, mm3_txen_n, _NA),
	_PINMUX_PIN_DEFEX(0x018C, mcbsp1_clkr, mcspi4_clk,   sim_cd,        _NA,        gpio_156, _NA,              _NA,        _NA),
	_PINMUX_PIN_DEFEX(0x018E, mcbsp1_fsr,  _NA,          cam_global_res, _NA,       gpio_157, _NA,              _NA,        _NA),
	_PINMUX_PIN_DEFEX(0x0190, mcbsp1_dx,   mcspi4_simo,  mcbsp3_dx,      _NA,       gpio_158, _NA,              _NA,        _NA),
	_PINMUX_PIN_DEFEX(0x0192, mcbsp1_dr,   mcspi4_somi,  mcbsp3_dr,      _NA,       gpio_159, _NA,              _NA,        _NA),
	_PINMUX_PIN_DEFEX(0x0194, mcbsp_clks,  cam_shutter,  _NA,            _NA,       gpio_160, uart1_cts,        _NA,        _NA),
	_PINMUX_PIN_DEFEX(0x0196, mcbsp1_fsx,  mcspi4_cs0,   mcbsp3_fsx,     _NA,       gpio_161, _NA,              _NA,        _NA),
	_PINMUX_PIN_DEFEX(0x0198, mcbsp1_clkx, mcbsp3_clkx,  _NA,            _NA,       gpio_162, _NA,              _NA,        _NA),
};

#endif

#define CONTROL_PADCONF_SDRC_D0			0x0030
#define CONTROL_PADCONF_SDRC_D1			0x0032
#define CONTROL_PADCONF_SDRC_D2			0x0034
#define CONTROL_PADCONF_SDRC_D3			0x0036
#define CONTROL_PADCONF_SDRC_D4			0x0038
#define CONTROL_PADCONF_SDRC_D5			0x003A
#define CONTROL_PADCONF_SDRC_D6			0x003C
#define CONTROL_PADCONF_SDRC_D7			0x003E
#define CONTROL_PADCONF_SDRC_D8			0x0040
#define CONTROL_PADCONF_SDRC_D9			0x0042
#define CONTROL_PADCONF_SDRC_D10		0x0044
#define CONTROL_PADCONF_SDRC_D11		0x0046
#define CONTROL_PADCONF_SDRC_D12		0x0048
#define CONTROL_PADCONF_SDRC_D13		0x004A
#define CONTROL_PADCONF_SDRC_D14		0x004C
#define CONTROL_PADCONF_SDRC_D15		0x004E
#define CONTROL_PADCONF_SDRC_D16		0x0050
#define CONTROL_PADCONF_SDRC_D17		0x0052
#define CONTROL_PADCONF_SDRC_D18		0x0054
#define CONTROL_PADCONF_SDRC_D19		0x0056
#define CONTROL_PADCONF_SDRC_D20		0x0058
#define CONTROL_PADCONF_SDRC_D21		0x005A
#define CONTROL_PADCONF_SDRC_D22		0x005C
#define CONTROL_PADCONF_SDRC_D23		0x005E
#define CONTROL_PADCONF_SDRC_D24		0x0060
#define CONTROL_PADCONF_SDRC_D25		0x0062
#define CONTROL_PADCONF_SDRC_D26		0x0064
#define CONTROL_PADCONF_SDRC_D27		0x0066
#define CONTROL_PADCONF_SDRC_D28		0x0068
#define CONTROL_PADCONF_SDRC_D29		0x006A
#define CONTROL_PADCONF_SDRC_D30		0x006C
#define CONTROL_PADCONF_SDRC_D31		0x006E
#define CONTROL_PADCONF_SDRC_CLK		0x0070
#define CONTROL_PADCONF_SDRC_DQS0		0x0072
#define CONTROL_PADCONF_SDRC_CKE0		0x0262
#define CONTROL_PADCONF_SDRC_CKE1		0x0264
#define CONTROL_PADCONF_SDRC_DQS1		0x0074
#define CONTROL_PADCONF_SDRC_DQS2		0x0076
#define CONTROL_PADCONF_SDRC_DQS3		0x0078

#define CONTROL_PADCONF_GPMC_A1			0x007A
#define CONTROL_PADCONF_GPMC_A2			0x007C
#define CONTROL_PADCONF_GPMC_A3			0x007E
#define CONTROL_PADCONF_GPMC_A4			0x0080
#define CONTROL_PADCONF_GPMC_A5			0x0082
#define CONTROL_PADCONF_GPMC_A6			0x0084
#define CONTROL_PADCONF_GPMC_A7			0x0086
#define CONTROL_PADCONF_GPMC_A8			0x0088
#define CONTROL_PADCONF_GPMC_A9			0x008A
#define CONTROL_PADCONF_GPMC_A10		0x008C
#define CONTROL_PADCONF_GPMC_A11		0x008E
#define CONTROL_PADCONF_GPMC_D1			0x0090
#define CONTROL_PADCONF_GPMC_D2			0x0092
#define CONTROL_PADCONF_GPMC_D3			0x0094
#define CONTROL_PADCONF_GPMC_D4			0x0096
#define CONTROL_PADCONF_GPMC_D5			0x0098
#define CONTROL_PADCONF_GPMC_D6			0x009A
#define CONTROL_PADCONF_GPMC_D7			0x009C
#define CONTROL_PADCONF_GPMC_D8			0x009E
#define CONTROL_PADCONF_GPMC_D9			0x00A0
#define CONTROL_PADCONF_GPMC_D10		0x00A2
#define CONTROL_PADCONF_GPMC_D11		0x00A4
#define CONTROL_PADCONF_GPMC_D12		0x00A6
#define CONTROL_PADCONF_GPMC_D13		0x00A8
#define CONTROL_PADCONF_GPMC_D14		0x00AA
#define CONTROL_PADCONF_GPMC_D15		0x00AC
#define CONTROL_PADCONF_GPMC_NCS0		0x00AE
#define CONTROL_PADCONF_GPMC_NCS1		0x00B0
#define CONTROL_PADCONF_GPMC_NCS2		0x00B2
#define CONTROL_PADCONF_GPMC_NCS3		0x00B4
#define CONTROL_PADCONF_GPMC_NCS4		0x00B6
#define CONTROL_PADCONF_GPMC_NCS5		0x00B8
#define CONTROL_PADCONF_GPMC_NCS6		0x00BA
#define CONTROL_PADCONF_GPMC_NCS7		0x00BC
#define CONTROL_PADCONF_GPMC_CLK		0x00BE
#define CONTROL_PADCONF_GPMC_NADV_ALE	0x00C0
#define CONTROL_PADCONF_GPMC_NOE		0x00C2
#define CONTROL_PADCONF_GPMC_NWE		0x00C4
#define CONTROL_PADCONF_GPMC_NBE0_CLE	0x00C6
#define CONTROL_PADCONF_GPMC_NBE1		0x00C8
#define CONTROL_PADCONF_GPMC_NWP		0x00CA
#define CONTROL_PADCONF_GPMC_WAIT0		0x00CC
#define CONTROL_PADCONF_GPMC_WAIT1		0x00CE
#define CONTROL_PADCONF_GPMC_WAIT2		0x00D0
#define CONTROL_PADCONF_GPMC_WAIT3		0x00D2

#define CONTROL_PADCONF_DSS_PCLK		0x00D4
#define CONTROL_PADCONF_DSS_HSYNC		0x00D6
#define CONTROL_PADCONF_DSS_VSYNC		0x00D8
#define CONTROL_PADCONF_DSS_ACBIAS		0x00DA
#define CONTROL_PADCONF_DSS_DATA0		0x00DC
#define CONTROL_PADCONF_DSS_DATA1		0x00DE
#define CONTROL_PADCONF_DSS_DATA2		0x00E0
#define CONTROL_PADCONF_DSS_DATA3		0x00E2
#define CONTROL_PADCONF_DSS_DATA4		0x00E4
#define CONTROL_PADCONF_DSS_DATA5		0x00E6
#define CONTROL_PADCONF_DSS_DATA6		0x00E8
#define CONTROL_PADCONF_DSS_DATA7		0x00EA
#define CONTROL_PADCONF_DSS_DATA8		0x00EC
#define CONTROL_PADCONF_DSS_DATA9		0x00EE
#define CONTROL_PADCONF_DSS_DATA10		0x00F0
#define CONTROL_PADCONF_DSS_DATA11		0x00F2
#define CONTROL_PADCONF_DSS_DATA12		0x00F4
#define CONTROL_PADCONF_DSS_DATA13		0x00F6
#define CONTROL_PADCONF_DSS_DATA14		0x00F8
#define CONTROL_PADCONF_DSS_DATA15		0x00FA
#define CONTROL_PADCONF_DSS_DATA16		0x00FC
#define CONTROL_PADCONF_DSS_DATA17		0x00FE
#define CONTROL_PADCONF_DSS_DATA18		0x0100
#define CONTROL_PADCONF_DSS_DATA19		0x0102
#define CONTROL_PADCONF_DSS_DATA20		0x0104
#define CONTROL_PADCONF_DSS_DATA21		0x0106
#define CONTROL_PADCONF_DSS_DATA22		0x0108
#define CONTROL_PADCONF_DSS_DATA23		0x010A

#define CONTROL_PADCONF_CAM_HS			0x010C
#define CONTROL_PADCONF_CAM_VS			0x010E
#define CONTROL_PADCONF_CAM_XCLKA		0x0110
#define CONTROL_PADCONF_CAM_PCLK		0x0112
#define CONTROL_PADCONF_CAM_FLD			0x0114
#define CONTROL_PADCONF_CAM_D0			0x0116
#define CONTROL_PADCONF_CAM_D1			0x0118
#define CONTROL_PADCONF_CAM_D2			0x011A
#define CONTROL_PADCONF_CAM_D3			0x011C
#define CONTROL_PADCONF_CAM_D4			0x011E
#define CONTROL_PADCONF_CAM_D5			0x0120
#define CONTROL_PADCONF_CAM_D6			0x0122
#define CONTROL_PADCONF_CAM_D7			0x0124
#define CONTROL_PADCONF_CAM_D8			0x0126
#define CONTROL_PADCONF_CAM_D9			0x0128
#define CONTROL_PADCONF_CAM_D10			0x012A
#define CONTROL_PADCONF_CAM_D11			0x012C
#define CONTROL_PADCONF_CAM_XCLKB		0x012E
#define CONTROL_PADCONF_CAM_WEN			0x0130
#define CONTROL_PADCONF_CAM_STROBE		0x0132

#define CONTROL_PADCONF_CSI2_DX0		0x0134
#define CONTROL_PADCONF_CSI2_DY0		0x0136
#define CONTROL_PADCONF_CSI2_DX1		0x0138
#define CONTROL_PADCONF_CSI2_DY1		0x013A

#define CONTROL_PADCONF_MMC1_CLK		0x0144
#define CONTROL_PADCONF_MMC1_CMD		0x0146
#define CONTROL_PADCONF_MMC1_DAT0		0x0148
#define CONTROL_PADCONF_MMC1_DAT1		0x014A
#define CONTROL_PADCONF_MMC1_DAT2		0x014C
#define CONTROL_PADCONF_MMC1_DAT3		0x014E
#define CONTROL_PADCONF_MMC1_DAT4		0x0150
#define CONTROL_PADCONF_MMC1_DAT5		0x0152
#define CONTROL_PADCONF_MMC1_DAT6		0x0154
#define CONTROL_PADCONF_MMC1_DAT7		0x0156

#define CONTROL_PADCONF_MMC2_CLK		0x0158
#define CONTROL_PADCONF_MMC2_CMD		0x015A
#define CONTROL_PADCONF_MMC2_DAT0		0x015C
#define CONTROL_PADCONF_MMC2_DAT1		0x015C
#define CONTROL_PADCONF_MMC2_DAT2		0x0160
#define CONTROL_PADCONF_MMC2_DAT3		0x0160
#define CONTROL_PADCONF_MMC2_DAT4		0x0164
#define CONTROL_PADCONF_MMC2_DAT5		0x0164
#define CONTROL_PADCONF_MMC2_DAT6		0x0168
#define CONTROL_PADCONF_MMC2_DAT7		0x0168

#define CONTROL_PADCONF_UART1_TX		0x017C
#define CONTROL_PADCONF_UART1_RTS		0x017E
#define CONTROL_PADCONF_UART1_CTS		0x0180
#define CONTROL_PADCONF_UART1_RX		0x0182
#define CONTROL_PADCONF_UART2_CTS		0x0174
#define CONTROL_PADCONF_UART2_RTS		0x0176
#define CONTROL_PADCONF_UART2_TX		0x0178
#define CONTROL_PADCONF_UART2_RX		0x017A
#define CONTROL_PADCONF_UART3_CTS_RCTX	0x019A
#define CONTROL_PADCONF_UART3_RTS_SD	0x019C
#define CONTROL_PADCONF_UART3_RX_IRRX	0x019E
#define CONTROL_PADCONF_UART3_TX_IRTX	0x01A0

#define CONTROL_PADCONF_MCBSP1_CLKR		0x018C
#define CONTROL_PADCONF_MCBSP1_FSR		0x018E
#define CONTROL_PADCONF_MCBSP1_DX		0x0190
#define CONTROL_PADCONF_MCBSP1_DR		0x0192
#define CONTROL_PADCONF_MCBSP_CLKS		0x0194
#define CONTROL_PADCONF_MCBSP1_FSX		0x0196
#define CONTROL_PADCONF_MCBSP1_CLKX		0x0198
#define CONTROL_PADCONF_MCBSP2_FSX		0x013C
#define CONTROL_PADCONF_MCBSP2_CLKX		0x013E
#define CONTROL_PADCONF_MCBSP2_DR		0x0140
#define CONTROL_PADCONF_MCBSP2_DX		0x0142
#define CONTROL_PADCONF_MCBSP3_DX		0x016C
#define CONTROL_PADCONF_MCBSP3_DR		0x016E
#define CONTROL_PADCONF_MCBSP3_CLKX		0x0170
#define CONTROL_PADCONF_MCBSP3_FSX		0x0172
#define CONTROL_PADCONF_MCBSP4_CLKX		0x0184
#define CONTROL_PADCONF_MCBSP4_DR		0x0186
#define CONTROL_PADCONF_MCBSP4_DX		0x0188
#define CONTROL_PADCONF_MCBSP4_FSX		0x018A

#define CONTROL_PADCONF_HSUSB0_CLK		0x01A2
#define CONTROL_PADCONF_HSUSB0_STP		0x01A4
#define CONTROL_PADCONF_HSUSB0_DIR		0x01A6
#define CONTROL_PADCONF_HSUSB0_NXT		0x01A8
#define CONTROL_PADCONF_HSUSB0_DATA0	0x01AA
#define CONTROL_PADCONF_HSUSB0_DATA1	0x01AC
#define CONTROL_PADCONF_HSUSB0_DATA2	0x01AE
#define CONTROL_PADCONF_HSUSB0_DATA3	0x01B0
#define CONTROL_PADCONF_HSUSB0_DATA4	0x01B2
#define CONTROL_PADCONF_HSUSB0_DATA5	0x01B4
#define CONTROL_PADCONF_HSUSB0_DATA6	0x01B6
#define CONTROL_PADCONF_HSUSB0_DATA7	0x01B8

#define CONTROL_PADCONF_I2C1_SCL		0x01BA
#define CONTROL_PADCONF_I2C1_SDA		0x01BC
#define CONTROL_PADCONF_I2C2_SCL		0x01BE
#define CONTROL_PADCONF_I2C2_SDA		0x01C0
#define CONTROL_PADCONF_I2C3_SCL		0x01C2
#define CONTROL_PADCONF_I2C3_SDA		0x01C4
#define CONTROL_PADCONF_I2C4_SCL		0x0A00
#define CONTROL_PADCONF_I2C4_SDA		0x0A02

#define CONTROL_PADCONF_HDQ_SIO			0x01C6
#define CONTROL_PADCONF_MCSPI1_CLK		0x01C8
#define CONTROL_PADCONF_MCSPI1_SIMO		0x01CA
#define CONTROL_PADCONF_MCSPI1_SOMI		0x01CC
#define CONTROL_PADCONF_MCSPI1_CS0		0x01CE
#define CONTROL_PADCONF_MCSPI1_CS1		0x01D0
#define CONTROL_PADCONF_MCSPI1_CS2		0x01D2
#define CONTROL_PADCONF_MCSPI1_CS3		0x01D4
#define CONTROL_PADCONF_MCSPI2_CLK		0x01D6
#define CONTROL_PADCONF_MCSPI2_SIMO		0x01D8
#define CONTROL_PADCONF_MCSPI2_SOMI		0x01DA
#define CONTROL_PADCONF_MCSPI2_CS0		0x01DC
#define CONTROL_PADCONF_MCSPI2_CS1		0x01DE

#define CONTROL_PADCONF_ETK_CLK			0x05D8
#define CONTROL_PADCONF_ETK_CTL			0x05DA
#define CONTROL_PADCONF_ETK_D0			0x05DC
#define CONTROL_PADCONF_ETK_D1			0x05DE
#define CONTROL_PADCONF_ETK_D2			0x05E0
#define CONTROL_PADCONF_ETK_D3			0x05E2
#define CONTROL_PADCONF_ETK_D4			0x05E4
#define CONTROL_PADCONF_ETK_D5			0x05E6
#define CONTROL_PADCONF_ETK_D6			0x05E8
#define CONTROL_PADCONF_ETK_D7			0x05EA
#define CONTROL_PADCONF_ETK_D8			0x05EC
#define CONTROL_PADCONF_ETK_D9			0x05EE
#define CONTROL_PADCONF_ETK_D10			0x05F0
#define CONTROL_PADCONF_ETK_D11			0x05F2
#define CONTROL_PADCONF_ETK_D12			0x05F4
#define CONTROL_PADCONF_ETK_D13			0x05F6
#define CONTROL_PADCONF_ETK_D14			0x05F8
#define CONTROL_PADCONF_ETK_D15			0x05FA

#define CONTROL_PADCONF_SAD2D_MCAD0		0x01E4
#define CONTROL_PADCONF_SAD2D_MCAD1		0x01E6
#define CONTROL_PADCONF_SAD2D_MCAD2		0x01E8
#define CONTROL_PADCONF_SAD2D_MCAD3		0x01EA
#define CONTROL_PADCONF_SAD2D_MCAD4		0x01EC
#define CONTROL_PADCONF_SAD2D_MCAD5		0x01EE
#define CONTROL_PADCONF_SAD2D_MCAD6		0x01F0
#define CONTROL_PADCONF_SAD2D_MCAD7		0x01F2
#define CONTROL_PADCONF_SAD2D_MCAD8		0x01F4
#define CONTROL_PADCONF_SAD2D_MCAD9		0x01F6
#define CONTROL_PADCONF_SAD2D_MCAD10	0x01F8
#define CONTROL_PADCONF_SAD2D_MCAD11	0x01FA
#define CONTROL_PADCONF_SAD2D_MCAD12	0x01FC
#define CONTROL_PADCONF_SAD2D_MCAD13	0x01FE
#define CONTROL_PADCONF_SAD2D_MCAD14	0x0200
#define CONTROL_PADCONF_SAD2D_MCAD15	0x0202
#define CONTROL_PADCONF_SAD2D_MCAD16	0x0204
#define CONTROL_PADCONF_SAD2D_MCAD17	0x0206
#define CONTROL_PADCONF_SAD2D_MCAD18	0x0208
#define CONTROL_PADCONF_SAD2D_MCAD19	0x020A
#define CONTROL_PADCONF_SAD2D_MCAD20	0x020C
#define CONTROL_PADCONF_SAD2D_MCAD21	0x020E
#define CONTROL_PADCONF_SAD2D_MCAD22	0x0210
#define CONTROL_PADCONF_SAD2D_MCAD23	0x0212
#define CONTROL_PADCONF_SAD2D_MCAD24	0x0214
#define CONTROL_PADCONF_SAD2D_MCAD25	0x0216
#define CONTROL_PADCONF_SAD2D_MCAD26	0x0218
#define CONTROL_PADCONF_SAD2D_MCAD27	0x021A
#define CONTROL_PADCONF_SAD2D_MCAD28	0x021C
#define CONTROL_PADCONF_SAD2D_MCAD29	0x021E
#define CONTROL_PADCONF_SAD2D_MCAD30	0x0220
#define CONTROL_PADCONF_SAD2D_MCAD31	0x0222
#define CONTROL_PADCONF_SAD2D_MCAD32	0x0224
#define CONTROL_PADCONF_SAD2D_MCAD33	0x0226
#define CONTROL_PADCONF_SAD2D_MCAD34	0x0228
#define CONTROL_PADCONF_SAD2D_MCAD35	0x022A
#define CONTROL_PADCONF_SAD2D_MCAD36	0x022C
#define CONTROL_PADCONF_SAD2D_CLK26MI	0x022E
#define CONTROL_PADCONF_SAD2D_NRESPWRON	0x0230
#define CONTROL_PADCONF_SAD2D_NRESPWARM	0x0232
#define CONTROL_PADCONF_SAD2D_ARMNIRQ	0x0234
#define CONTROL_PADCONF_SAD2D_UMAFIQ	0x0236
#define CONTROL_PADCONF_SAD2D_SPINT		0x0238
#define CONTROL_PADCONF_SAD2D_FRINT		0x023A
#define CONTROL_PADCONF_SAD2D_DMAREQ0	0x023C
#define CONTROL_PADCONF_SAD2D_DMAREQ1	0x023E
#define CONTROL_PADCONF_SAD2D_DMAREQ2	0x0240
#define CONTROL_PADCONF_SAD2D_DMAREQ3	0x0242
#define CONTROL_PADCONF_SAD2D_NTRST		0x0244
#define CONTROL_PADCONF_SAD2D_TDI		0x0246
#define CONTROL_PADCONF_SAD2D_TDO		0x0248
#define CONTROL_PADCONF_SAD2D_TMS		0x024A
#define CONTROL_PADCONF_SAD2D_TCK		0x024C
#define CONTROL_PADCONF_SAD2D_RTCK		0x024E
#define CONTROL_PADCONF_SAD2D_MSTDBY	0x0250
#define CONTROL_PADCONF_SAD2D_IDLEREQ	0x0252
#define CONTROL_PADCONF_SAD2D_IDLEACK	0x0254
#define CONTROL_PADCONF_SAD2D_MWRITE	0x0256
#define CONTROL_PADCONF_SAD2D_SWRITE	0x0258
#define CONTROL_PADCONF_SAD2D_MREAD		0x025A
#define CONTROL_PADCONF_SAD2D_SREAD		0x025C
#define CONTROL_PADCONF_SAD2D_MBUSFLAG	0x025E
#define CONTROL_PADCONF_SAD2D_SBUSFLAG	0x0260
#define CONTROL_PADCONF_SAD2D_SWAKEUP	0x0A4C

#define CONTROL_PADCONF_SYS_32K			0x0A04
#define CONTROL_PADCONF_SYS_CLKREQ		0x0A06
#define CONTROL_PADCONF_SYS_NRESWARM	0x0A08
#define CONTROL_PADCONF_SYS_BOOT0		0x0A0A
#define CONTROL_PADCONF_SYS_BOOT1		0x0A0C
#define CONTROL_PADCONF_SYS_BOOT2		0x0A0E
#define CONTROL_PADCONF_SYS_BOOT3		0x0A10
#define CONTROL_PADCONF_SYS_BOOT4		0x0A12
#define CONTROL_PADCONF_SYS_BOOT5		0x0A14
#define CONTROL_PADCONF_SYS_BOOT6		0x0A16
#define CONTROL_PADCONF_SYS_OFF_MODE	0x0A18
#define CONTROL_PADCONF_SYS_CLKOUT1		0x0A1A
#define CONTROL_PADCONF_SYS_NIRQ		0x01E0
#define CONTROL_PADCONF_SYS_CLKOUT2		0x01E2

#define CONTROL_PADCONF_JTAG_NTRST		0x0A1C
#define CONTROL_PADCONF_JTAG_TCK		0x0A1E
#define CONTROL_PADCONF_JTAG_TMS_TMSC	0x0A20
#define CONTROL_PADCONF_JTAG_TDI		0x0A22
#define CONTROL_PADCONF_JTAG_EMU0		0x0A24
#define CONTROL_PADCONF_JTAG_EMU1		0x0A26
#define CONTROL_PADCONF_JTAG_RTCK		0x0A4E
#define CONTROL_PADCONF_JTAG_TDO		0x0A50




int
omap3_scm_padconf_set(uint32_t padconf, unsigned int mode, unsigned int state);

int
omap3_scm_padconf_set_gpiomode(uint32_t gpio, unsigned int state);


int
omap3_scm_padconf_get(uint32_t padconf, unsigned int *mode, unsigned int *state);



#endif /* _OMAP3_PINMUX_H_ */
